Vertical Twin Bit (VTB) failures are commonly observed in memories. A VTB failure refers to the failure of two bits that are in neighboring rows, and possibly in the same column. Statistic results have shown that among all Static Random Access Memory (SRAM) failures, single-bit failures have the highest rate of 67.4 percent, followed by the VTB failure rate of about 12.1 percent. Therefore, row redundancy was provided to solve the VTB failures, wherein two redundant rows were provided to fix a VTB failure.
When VTB failures are found, and the failed bits are indentified, the rows (referred to as failed rows hereinafter) in which the failed bits are located are replaced by the redundant rows. For a VTB failure, two redundant rows are needed, each replacing one of the failed rows. The addresses of the failed rows need to be stored, so that each time a read operation is performed to one of the failed rows, the data are read from the respective redundant rows instead. Similarly, each time a write operation is performed to one of the failed rows, the data to be written are actually written into the respective one of the redundant rows instead.
Each of the addresses of the failed rows was typically stored in a set of D flip-flops. In addition, the set of D flip-flops also includes an addition D flip-flop storing an “Enable” bit in a separate D flip-flop. A “true” in the “Enable” bit indicates that this set of D flip-flops is enabled to store a row address. Two sets of D flip-flops are needed, each corresponding to one of the two failed rows.
A comparator is provided for each set of D flip-flops, and for each of the read/write operations, the row address corresponding to the read/write operation is compared to the row address stored in the respective D flip-flops. If the row address of the read/write operation matches the row address stored in the respective D flip-flops, a hit is found, and the row on which the read/write operation is performed is replaced with a respective redundant row.
The number of D flip-flops in each set is equal to (log2 N)+1, wherein “N” is an integer representing the total number of rows in the memory, and integer “1” represents the D flip-flop used by the “Enable” bit. For example, for a memory array having 2048 rows, each set of D flip-flops needs 12 D flip-flops. Since there are two failed rows involved in a VTB failure, 24 D flip-flops are needed. Therefore, by using this method, although the coverage for repairing VTB failures is 100 percent, the chip area penalty for forming two sets of D flip-flops is also high.
In another method, the row address stored in the D flip-flops does not include the least significant bit (LSB) of the failed row(s). The remaining bits of the row address (referred to as upper bits hereinafter) are stored in the D flip-flops. Since the LSB can be either “1” or “0,” the stored upper bits of the row address correspond to two row addresses. In this method, only one set of row address is stored, and one comparator is provided, which compares the upper bits of the row address of the row on which the read/write operation is performed with the upper bits of the row address stored in the D flip-flops. The LSBs are not compared.
This method, however, can only be used to repair two neighboring rows whose upper bits are identical. If the upper bits of two failed neighboring rows are different, the stored row address can only record one of the failed rows, and the repair coverage is 50 percent. For example, if the VTB failure occurs in rows [0000] and [0001], since their upper bits are both [000], the failure for both rows can be repaired. If the VTB failure occurs in rows [0010] and [0011], since their upper bits are both [001], the failure can also be repaired. However, if the VTB failure occurs in rows [0001] and [0010], although these two rows are neighboring rows, since their upper bits are [000] and [001], the D flip-flops can only record one of [000] and [001]. As a result, only one of failed rows [0001] and [0010] can be repaired, and the other cannot be repaired. For this method, the reduction in the chip area usage occurs with the cost of reliability.